1. Field of the Invention
The present invention relates to a delay-locked loop and a method for a delay-locked loop generating an application clock, and particularly to a delay-locked loop and a method for a delay-locked loop generating an application clock that can be applied to an advanced dynamic random access memory, and not amplify noise within a dynamic random access memory.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a delay-locked loop 100 according to the prior art. The delay-locked loop 100 includes a first delay unit 102, a replica delay unit 104, a phase detector 106, and a controller 108. As shown in FIG. 1, the first delay unit 102 generates a delay clock DCLK according to an input clock XCLK and a first delay time T1 of the first delay unit 102. The replica delay unit 104 generates a feedback clock FCLK according to the delay clock DCLK and a replica delay time RDT of the replica delay unit 104, where a sum of the first delay time T1 and the replica delay time RDT is equal to a period of the input clock XCLK. The phase detector 106 receives the input clock XCLK and the feedback clock FCLK, and generates a phase detection signal PDS according to a difference between a phase of the input clock XCLK and a phase of the feedback clock FCLK. The controller 108 is coupled to the phase detector 106 for generating a phase control signal PCS to the first delay unit 102 according to the phase detection signal PDS. Thus, the first delay unit 102 can adjust the first delay time T1 according to the phase control signal PCS. That is to say, the first delay unit 102 can adjust a phase of the delay clock DCLK according to the phase control signal PCS. As shown in FIG. 1, the delay clock DCLK is outputted to an internal delay unit 110 of an application circuit, and the internal delay unit 110 can generate an output data clock DQ of the application circuit (e.g. an output data clock of a dynamic random access memory) according to an internal delay time IT of the application circuit and the delay clock DCLK, where the internal delay time IT is the same as the replica delay time RDT.
Please refer to FIG. 2. FIG. 2 is a diagram illustrating relationships of the input clock XCLK, the feedback clock FCLK, and the output data clock DQ. As shown in FIG. 2, because the sum of the first delay time T1 and the replica delay time RDT is equal to the period of the input clock XCLK, when the delay-locked loop 100 is locked, the phase of the feedback clock FCLK and the phase of the input clock XCLK are in phase (or the delay-locked loop 100 locks the difference between the phase of the input clock XCLK and the phase of the feedback clock FCLK at a fixed difference). In addition, because the internal delay time IT is the same as the replica delay time RDT, a sum of the first delay time T1 and the internal delay time IT is also equal to the period of the input clock XCLK. Therefore, a rising edge of the output data clock DQ can be synchronized with a rising edge of the input clock XCLK.
Please refer to FIG. 3. FIG. 3 is a diagram illustrating relationships of the input clock XCLK and the output data clock DQ in an advanced dynamic random access memory process. As shown in FIG. 3, the period of the input clock XCLK is decreased significantly, but the internal delay time IT is not decreased significantly synchronously. Although, a designer can still extend the first delay time T1 to make the rising edge of the feedback clock FCLK be aligned in a rising edge of a next input clock XCLK for a phase of the output data clock DQ and the phase of the input clock XCLK being in phase, a total delay of the delay-locked loop 100 can be longer than the period of the input clock XCLK, resulting in noise within the dynamic random access memory being amplified. Therefore, the delay-locked loop 100 is not proper to the advanced dynamic random access memory process.